Mixed mode compensation circuit

ABSTRACT

A mixed mode compensation circuit for a power converter generate a digital signal according to a reference signal and a feedback signal which is related to the output voltage of the power converter, convert the digital signal into a first analog signal, offset the first analog signal with a variable offset value to generate a second analog signal, and filter out high-frequency components of the second analog signal to generate a third analog signal for stable output voltage of the power converter. The mixed mode compensation does not require large capacitors, and thus the circuit can be integrated into an integrated circuit.

CROSS REFERENCE

The present invention is a continuation-in-part application of U.S. Ser.No. 13/672,125, filed on Nov. 8, 2012.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention is related generally to a power converter and,more particularly, to a compensation circuit and method for a powerconverter.

2. Description of Related Art

A feedback loop of a power converter needs a compensation circuit tocompensate the phase margin for stability of the feedback loop.Conventional analog compensation circuits include an EA typecompensation circuit 10 as shown in FIG. 1 or a gm type compensationcircuit 14 as shown in FIG. 2. Referring to FIG. 1, the EA typecompensation circuit 10 includes an error amplifier 12, a capacitor C1and a resistor R3 serially connected between an inverting input terminaland an output terminal of the error amplifier 12, and a resistor R4parallel connected with the serially connected capacitor C1 and resistorR3. The error amplifier 12 amplifies the difference between a feedbacksignal Vfb and a reference signal Vref to generate a signal Vcomp whichis then provided to a power converter to stabilize the output voltage Voof the power converter. The resistors R3 and R4 and the capacitor C1 areconfigured to compensate the signal Vcomp. Some applications may notinclude the resistor R4 shown in FIG. 1. Referring to FIG. 2, the gmtype compensation circuit 14 includes a transconductance amplifier 16, aresistor R3 and a capacitor C1 serially connected between an outputterminal of the transconductance amplifier 16 and a ground terminal GND,and a capacitor C2 parallel connected with the serially connectedresistor R3 and capacitor C1. The transconductance amplifier 16 convertsthe difference between a feedback signal Vfb and a reference signal Vrefinto a current Icomp. The resistor R3 and the capacitors C1 and C2 areconfigured to generate a compensation signal Vcomp according to thecurrent Icomp. For a control integrated circuit (IC), using an externalcompensation circuit requires a pin of the control IC. In order toreduce the number of the pins of a control IC, more and more solutionsintegrate a compensation circuit into a control IC, for example, U.S.Pat. No. 7,504,888. Generally speaking, the gm type compensation circuit14 is easier to be integrated into a control IC, while this type ofsolutions also has many limitations. Generally, a control IC for a highswitching frequency DC/DC power converter has a pole and a zero pointthat are both higher than 10 KHz, so it is easier to integrate thecompensation circuit into the control IC. However, in low-bandwidthapplications such as power factor correction (PFC) power converters orother similar PFC control ICs or power converters, the compensationcircuit 14 requires large capacitors C1 and C2. Under consideration ofcosts and chip area, it is much difficult to integrate the largecapacitors C1 and C2 into the control IC completely. More specifically,the input voltage of a PFC power converter is an alternating-current(AC) voltage with an AC frequency of 60 Hz, so a control IC needs a lowgain and a pole and a zero point of a low frequency to achieve alow-bandwidth loop to filter out the AC frequency. Therefore, thecompensation circuit 14 requires large capacitors C1 and C2 forcompensation to make the signal Vcomp vary slowly so as to filter outthe AC frequency. However, the large capacitors C1 and C2 satisfying therequirements cannot be implemented in a control IC, the control IC isrequired a pin to be connected to external large capacitors C1 and C2.If it is desired to shrink the capacitors C1 and C2 so that they can beintegrated into a control IC, then it needs the current Icomp to bereduced to the nanoampere level or the picoampere level; however, such asmall current is much sensitive to the process and cannot be controlledaccurately, so it is difficult to integrate the large capacitors C1 andC2 into a control IC.

Since it is difficult to integrate an analog compensation circuit into acontrol IC, many digital compensation circuits are proposed, forexample, U.S. Pat. Nos. 7,743,266 and 7,894,218. Although these digitalcompensation circuits can be integrated into the control IC of a PFCpower converter, usually a complex digital signal processing (DSP)algorithm is needed and thus a large chip area is required, resulting inincreased costs and chip size. On the other hand, the slowly varyingsignal Vcomp will make a power converter unable to rapidly respond to aload transient, resulting in a large voltage drop or overshoot of theoutput voltage Vo.

SUMMARY OF THE INVENTION

In one aspect, the present invention provides a mixed mode compensationcircuit for a power converter, comprising: a digital signal generatorfor generating a first pole, the digital signal generator generating adigital signal according to a reference signal and a feedback signalwhich is related to an output voltage of the power converter; and adigital-to-analog converter coupled to the digital signal generator, forconverting the digital signal into a first analog signal.

In one embodiment, the mixed mode compensation circuit furthercomprises: an offset injector coupled to the digital-to-analog converterfor generating a zero, the offset injector providing a variable offsetvalue determined by a difference between the feedback signal and thereference signal to offset the first analog signal to generate a secondanalog signal.

In one embodiment, the mixed mode compensation circuit furthercomprises: a low-pass filter coupled to the digital-to-analog converterfor generating a second pole, the low-pass filter being configured tofilter out high-frequency components of the first analog signal togenerate a second analog signal.

In one embodiment, the mixed mode compensation circuit furthercomprises: an offset injector coupled to the digital-to-analogconverter, for providing a variable offset value determined by adifference between the feedback signal and the reference signal tooffset the first analog signal to generate a second analog signal; and alow-pass filter coupled to the offset injector, the low-pass filterbeing configured to filter out high-frequency components of the secondanalog signal to generate a third analog signal for the power converterto stabilize the output voltage.

In one embodiment, the mixed mode compensation circuit furthercomprises: a low-pass filter coupled to the digital-to-analog converter,the low-pass filter being configured to filter out high-frequencycomponents of the first analog signal to generate a second analogsignal; and an offset injector coupled to the low-pass filter, forproviding a variable offset value determined by a difference between thefeedback signal and the reference signal to offset the second analogsignal to generate a third analog signal for the power converter tostabilize the output voltage.

In one embodiment, the mixed mode compensation circuit furthercomprises: an offset injector coupled to the digital signal generator,for providing a variable offset value determined by a difference betweenthe feedback signal and the reference signal to offset the digitalsignal to generate a second analog signal; and an adder for adding thefirst analog signal and the second analog signal to generate a thirdanalog signal for the power converter to stabilize the output voltage.

In one embodiment, the mixed mode compensation circuit further comprisesa low-pass filter coupled to an output of the adder.

In one embodiment, the mixed mode compensation circuit furthercomprises: an offset injector coupled to the digital signal generator,for providing a variable offset value determined by a difference betweenthe feedback signal and the reference signal to offset the digitalsignal to generate a second analog signal; a low-pass filter coupled tothe offset injector, the low-pass filter being configured to filter outhigh-frequency components of the first analog signal to generate asecond analog signal; and an adder for adding the first analog signaland the third analog signal to generate a fourth analog signal for thepower converter to stabilize the output voltage.

In another aspect, the present invention provides a mixed modecompensation circuit for a power converter, comprising: a digital signalgenerator for generating a first digital signal and a second digitalsignal according to a reference signal and an output voltage feedbacksignal which is related to an output voltage of the power converter; adigital offset injector coupled to the digital signal generator, forgenerating a variable offset according to the second digital signal; anadder for adding the first digital signal and the variable offset or foradding the first digital signal and a signal related to the variableoffset; and a digital-to-analog converter coupled to the adder, forconverting an output of the adder or a signal related to the output ofthe adder into an analog signal.

In one embodiment, the mixed mode compensation circuit furthercomprises: a low-pass filter coupled to the digital-to-analog converterfor filtering out high-frequency components of the analog signal.

In one embodiment, the mixed mode compensation circuit furthercomprises: (1) a digital filter coupled between the digital offsetinjector and the adder for filtering the variable offset to generate thesignal related to the variable offset; or (2) a digital filter coupledbetween the adder and the digital-to-analog converter for filtering theoutput of the adder to generate the signal related to the output of theadder.

In one embodiment, the digital offset injector feedback controls a clocksignal of the digital signal generator.

In another aspect, the present invention provides a mixed modecompensation circuit for a power converter, comprising: a digital signalgenerator for generating a first digital signal and a second digitalsignal according to a reference signal and an output voltage feedbacksignal which is related to an output voltage of the power converter; adigital offset injector coupled to the digital signal generator, forgenerating a variable offset according to the second digital signal; afirst digital-to-analog converter coupled to the digital signalgenerator, for converting the first digital signal into a first analogsignal; a second digital-to-analog converter coupled to the digitalsignal generator, for converting the second digital signal into a secondanalog signal; and an adder for adding the first analog signal and thesecond analog signal or adding a signal related to the first analogsignal and the second analog signal.

In one embodiment, the mixed mode compensation circuit furthercomprises: a low-pass filter coupled between the first digital-to-analogconverter and the adder or coupled to the output of the adder.

In another aspect, the present invention provides a mixed modecompensation circuit for a power converter, comprising: a digital signalgenerator for generating a first digital signal according to a referencesignal and an output voltage feedback signal which is related to anoutput voltage of the power converter; a digital filter coupled to thedigital signal generator, for filtering the first digital signal; and adigital-to-analog converter coupled to the digital filter, forconverting an output of the digital filter into an analog signal.

In one embodiment, the digital signal generator includes: a SAR-ADC(Successive Approximation Register Analog to Digital Converter) forgenerating an up/down signal according to the output voltage feedbacksignal and the reference signal; and an up/down counter having an outputcontrolled by the up/down signal to correspondingly increase ordecrease.

In one embodiment, the digital offset injector generates a digitalnumber or code corresponding to α·(Vfb1−Vref1), wherein a is a positivereal number; Vfb1 is the output voltage feedback signal; and Vref1 isthe reference signal.

In one embodiment, the digital filter includes a D flip-flop or a movingaverage circuit.

The objectives, technical details, features, and effects of the presentinvention will be better understood with regard to the detaileddescription of the embodiments below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a conventional EA type compensationcircuit.

FIG. 2 is a circuit diagram of a conventional gm type compensationcircuit.

FIG. 3A shows a mixed mode compensation circuit according to the presentinvention.

FIGS. 3B-3H show other embodiments of mixed mode compensation circuitsaccording to the present invention.

FIG. 4 is a circuit diagram of an embodiment for the mixed modecompensation circuit shown in FIG. 3A.

FIG. 5 is a current-voltage characteristic curve of the transconductanceamplifier shown in FIG. 2.

FIG. 6 is a characteristic curve of the voltage variation rate dVa1/dtof the first signal Va1 shown in FIG. 4 versus the voltage Vref1−Vfb1.

FIG. 7 is a circuit diagram of another embodiment for the mixed modecompensation circuit shown in FIG. 3A.

FIG. 8 is a timing diagram of the clock signal and pulse signals shownin FIG. 7.

FIG. 9 is a characteristic curve of the voltage variation rate dVa1/dtof the first signal Va1 shown in FIG. 7 versus the voltage Vref1−Vfb1.

FIG. 10 is a circuit diagram of another embodiment for the mixed modecompensation circuit shown in FIG. 3A.

FIG. 11 shows the output voltages of the power converter and the signalsVcomp that are generated by using the gm type analog compensationcircuit shown in FIG. 2 and the mixed mode compensation circuitaccording to the present invention, respectively.

FIGS. 12A-12G show several other embodiments of the mixed modecompensation circuit according to the present invention.

FIG. 13 shows an embodiment of the digital signal generator 122.

FIGS. 14A-14D show four embodiments of the SAR-ADC 132.

FIG. 15 shows an embodiment of the up/down counting circuit 134.

FIGS. 16A-16I shows nine embodiments of the digital offset injector 126.

FIGS. 17A and 17B show two embodiments of the digital filter 128.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 3A, a mixed mode compensation circuit 20 according tothe present invention is disclosed, which is applicable to various typesof power converters such as a DC/DC power converter and a PFC powerconverter. In the mixed mode compensation circuit 20, a digital signalgenerator 22 generates a digital signal Sd according to a referencesignal Vref1 and a feedback signal Vfb1 related to the output voltage ofa power converter, a digital-to-analog converter (DAC) 24 converts thedigital signal Sd into a first signal Va1 which is an analog signal, anoffset injector 26 provides a variable offset value to offset the firstsignal Va1 to generate a second signal Va2 which is also an analogsignal, and a low-pass filter (LPF) 28 filters out the high-frequencycomponents of the second signal Va2 to generate a third signal Vcompwhich is then provided to stabilize the output voltage of the powerconverter. The mixed mode compensation circuit 20 simulates the gm typecompensation circuit 14 shown in FIG. 2. As is well known, the gm typecompensation circuit 14 provides two poles and a zero point, and themixed mode compensation circuit 20 can also provide two poles and a zeropoint. In detail, the digital signal generator 22 and the DAC 24 may beviewed as a first pole generator/compensator for providing a first pole,the offset injector 26 may be viewed as a zero pointgenerator/compensator for providing a zero point, and the LPF 28 may beviewed as a second pole generator/compensator for providing a secondpole.

Note that it may not be necessarily required to generate/compensate twopoles and one zero. In some applications, it may only be required togenerate/compensate one pole, or one pole and one zero, or two poles.FIGS. 3B-3D show mixed mode compensation circuits 20 a, 20 b and 20 ccorresponding to these applications. Furthermore, in the embodimentgenerating/compensating two poles and one zero, it is not necessary forthe LPF 28 to be located after the offset injector 26 and connected inseries with the digital signal generator 22 and the DAC 24; it can bearranged otherwise. For example, FIG. 3E shows an embodiment wherein theLPF 28 is located before the offset injector 26; FIG. 3F shows anembodiment wherein the offset injector 26 and the LPF 28 are located ina separated path to provide a compensation for a zero point and a secondpole, and an adder 29 adds the output signal from the DAC 24 with thecompensation signal generated in the separated path; FIG. 3G shows anembodiment which is similar to the embodiment of FIG. 3F but the LPF 28is omitted. In additional to the above arrangements, the LPF 28 can belocated at other locations such as but not limited to the location afterthe adder 29 (coupled to the output of the adder 29), as shown in theembodiment of FIG. 3H.

FIG. 4 is a circuit diagram of a first embodiment for the mixed modecompensation circuit 20 shown in FIG. 3A. In order to realize the firstpole of a low frequency, the digital signal generator 22 and the DAC 24are used to simulate the transconductance amplifier 16 of the gm typecompensation circuit 14 shown in FIG. 2. In the digital signal generator22 shown in FIG. 4, a comparator 30 compares the feedback signal Vfb1with the reference signal Vref1 to generate a comparison signal Sc1, aninverter 32 inverts the comparison signal Sc1 to generate a signal Sc2for a controller 42, an oscillator 40 provides a clock signal Clk forthe controller 42 and an up/down counter 44, and the controller 42samples the signal Sc2 responsive to the clock signal Clk to assertcontrol signals Up and Down for the up/down counter 44 to adjust thedigital signal Sd. When the sampling result indicates that the feedbacksignal Vfb1 is greater than the reference signal Vref1, the controller42 asserts the control signal Down to signal the up/down counter 44 todecrease the digital signal Sd by one bit so as to decrease the outputpower of the power converter. When the sampling result indicates thatthe feedback signal Vfb1 is smaller than the reference signal Vref1, thecontroller 42 asserts the control signal Up to signal the up/downcounter 44 to increase the digital signal Sd by one bit so as toincrease the output power of the power converter. The up/down counter 44samples the control signals Up and Down from the controller 42responsive to the clock signal Clk to adjust the digital signal Sd. TheDAC 24 converts the digital signal Sd into the first analog signal Val.The DAC 24 is a relatively common circuit, and thus the internal circuitand operations thereof will not be further described herein. When theclock signal Clk is at a low frequency, the sampling frequency isrelatively low and the digital signal Sd varies slowly, which makes thethird analog signal Vcomp outputted by the mixed mode compensationcircuit 20 vary slowly. This effect is the same as that in the casewhere the gm type compensation circuit 14 uses large capacitors C1 andC2.

If the third analog signal Vcomp outputted by the mixed modecompensation circuit 20 still varies slowly when a load transient occursto the power converter, then the power converter cannot make a responserapidly, causing the output voltage Vo of the power converter to have alarge voltage drop or overshoot. For this issue, the digital signalgenerator 22 shown in FIG. 4 further includes a hysteresis comparator 34to compare the feedback signal Vfb1 with a threshold VH1 to generate acomparison signal SH for the controller 42, a hysteresis comparator 36to compare the feedback signal Vfb1 with a threshold VL1 to generate acomparison signal SL for the controller 42, and an operationaltransconductance amplifier 38 to amplify the difference ΔV between thefeedback signal Vfb1 and the reference signal Vref1 to generate afrequency adjustment signal Sfm which is then provided to the oscillator40 to adjust the frequency of the clock signal Clk. When the differenceΔV between the feedback signal Vfb1 and the reference signal Vref1increases, the frequency adjustment signal Sfm will increase thefrequency of the clock signal Clk to increase the sampling frequency soas to speed up the variation of the digital signal Sd and the slew rateof the third analog signal Vcomp. When the feedback signal Vfb1 isgreater than the threshold VH1 or smaller than the threshold VL1, thehysteresis comparator 34 or 36 asserts the comparison signal SL or SHfor the oscillator 40 to increase the frequency of the clock signal Clkto a maximum value such that the digital signal Sd is increased ordecreased at a maximum frequency. Furthermore, when the feedback signalVfb1 is greater than the threshold VH1, the controller 42 responsive tothe comparison signal SL asserts a control signal Down_limit for theup/down counter 44 such that the up/down counter 44 decreases thedigital signal Sd to a minimum value at the maximum frequency to therebyincrease the slew rate of the third analog signal Vcomp, thus rapidlyreducing the output power of the power converter and rapidly reducingthe output voltage Vo of the power converter to a preset level.Likewise, when the feedback signal Vfb1 is smaller than the thresholdVL1, the controller 42 responsive to the comparison signal SH asserts acontrol signal Up limit for the up/down counter 44 such that the up/downcounter 44 increases the digital signal Sd to a maximum value at themaximum frequency to thereby increase the slew rate of the third analogsignal Vcomp, thus rapidly increasing the output power of the powerconverter and rapidly increasing the output voltage Vo of the powerconverter to the preset level. In other embodiments, when the feedbacksignal Vfb1 is greater than the threshold VH1 or smaller than thethreshold VL1, the up/down counter 44 can also adjust the digital signalSd responsive to the comparison signal SL or SH to the minimum value orthe maximum value immediately. When a load transient occurs, thedifference ΔV between the feedback signal Vfb1 and the reference signalVref1 increases, so the sampling frequency of the controller 42 and theup/down counter 44 is increased to thereby increase the slew rate of thethird analog signal Vcomp. Moreover, when the feedback signal Vfb1 isgreater than the threshold VH1 or smaller than the threshold VL1, thedigital signal Sd can be decreased to the minimum value or increased tothe maximum value immediately or at the maximum frequency, so the loadtransient response of the power converter can be improved effectively.

FIG. 5 is a current-voltage characteristic curve of the transconductanceamplifier 16 shown in FIG. 2. From the circuit shown in FIG. 2, it mayhave

Ce×Vcomp=Icomp×T,  [EQ-1]

where Ce is the equivalent capacitance of the capacitors C1 and C2, andT is the duration that the current Icomp is asserted. From the equationEQ-1, it is further derived

Icomp/Ce=Vcomp/T.  [EQ-2]

As can be known from the equation EQ-2, because the current Icomp andthe capacitance Ce determine the voltage variation rate dVcomp/dt andthe capacitance Ce is a constant value, the current Icomp is directlyproportional to the voltage variation rate dVcomp/dt. Therefore, the Yaxis in FIG. 5 may also be viewed to represent the voltage variationrate dVcomp/dt. The digital signal generator 22 and the DAC shown inFIG. 3A that simulate the transconductance amplifier 16 can also achievea similar voltage variation rate. For example, FIG. 6 is acharacteristic curve of the voltage variation rate dVa1/dt (i.e., theslew rate) of the first signal Va1 of the DAC 24 shown in FIG. 4 versusthe input voltage Vfb1 of the digital signal generator 22. Apart of thiscurve between the thresholds VL1 and VH1 is the same as the curve shownin FIG. 5, and there are hysteresis regions at two ends of this curve.When the feedback signal Vfb1 is increased to be greater than thethreshold VH1, the digital signal Sd is decreased at the maximumsampling frequency, so the first signal Va1 has a maximum negativevoltage variation rate −dVa1/dt_max and the voltage variation ratedVa1/dt of the first signal Va1 will not return to the original leveluntil the feedback signal Vfb1 is decreased to be smaller than ahysteresis threshold Vhy1. Likewise, when the feedback signal Vfb1 isdecreased to be smaller than the threshold VL1, the digital signal Sd isincreased at the maximum frequency of the clock signal Clk, so the firstsignal Va1 has a maximum positive voltage variation rate dVa1/dt_max andthe voltage variation rate dVa1/dt of the first signal Va1 will notreturn to the original level until the feedback signal Vfb1 is increasedto be greater than a hysteresis threshold Vhy2.

In the embodiment shown in FIG. 4, the offset injector 26 includes acurrent source 46 and a switch M1 connected in series between a powerterminal Vcc and a first terminal 54 of a resistor Rof, a current source48 and a switch M2 connected in series between the first terminal 54 ofthe resistor Rof and a ground terminal GND, a current source 50 and aswitch M3 connected in series between the power terminal Vcc and asecond terminal 56 of the resistor Rof, and a current source 52 and aswitch M4 connected in series between the second terminal 56 of theresistor Rof and the ground terminal GND. The switches M1 and M4 arecontrolled by the control signal Down from the controller 42, and theswitches M2 and M3 are controlled by the control signal Up from thecontroller 42. Controlling the switches M1, M2, M3 and M4 may determinethe direction of the current Iof of the resistor Rof. The currentsources 46, 48, 50 and 52 determine the magnitude of the current Iofaccording to the frequency adjustment signal Sfm from the operationaltransconductance amplifier 38 so as to determine a variable offset valueVof for offsetting the first signal Va1 to generate the second signalVa2. Because the frequency adjustment signal Sfm is associated with thedifference ΔV between the feedback signal Vfb1 and the reference signalVref1, the variable offset value Vof also varies with the difference ΔV.In other embodiments, the current sources 46, 48, 50 and 52 may alsodetermine the current Iof according to other signals associated with thedifference ΔV instead. The low-pass filter 28 shown in FIG. 4 includesan RC filter established by a resistor Rf and a capacitor Cf, andfilters the second signal Va2 to generate the third signal Vcomp. Fromthe viewpoint of physical significance of the control loop, the zeropoint of the gm type compensation circuit 14 serves as a phase leadcompensation and the second pole is similar to a low-pass filter, so themixed mode compensation circuit 20 of the present invention uses theoffset injector 26 to provide an instantaneous voltage variation tosimulate the function of the zero point and uses the RC filter toachieve the second pole.

FIG. 7 is a circuit diagram of a second embodiment for the mixed modecompensation circuit 20 shown in FIG. 3A. In the digital signalgenerator 22, a multiplexer 60 is configured to switch a threshold VH1,a threshold VH2, the reference signal Vref1, a threshold VL2 and athreshold VL1 in turn to a non-inverting input terminal of a comparator62 responsive to pulse signals Sp1-Sp5, respectively, whereVH1>VH2>Vref1>VL2>VL1, the comparator 62 has an inverting input terminalto receive the feedback signal Vfb1 and compares the feedback signalVfb1 with VH1, VH2, Vref1, VL1 and VL2 one by one to generate acomparison signal for the controller 42, and the controller 42 samplesthe comparison signal from the comparator 62 responsive to a clocksignal Clk and the pulse signals Sp1-Sp5, and asserts control signals Upand Down for the up/down counter 44 according to the sampling result soas to increase or decrease the digital signal Sd. The controller 42 alsoidentifies whether the feedback signal Vfb1 is greater than the maximumthreshold VH1 or smaller than the minimum threshold VL1 according to thecomparison results of the comparator 62. If the feedback signal Vfb1 isgreater than the maximum threshold VH1, then the controller 42 asserts acontrol signal Down_limit such that the up/down counter 44 decreases thedigital signal Sd to a minimum value immediately or at a maximumfrequency so as to increase the slew rate of the third analog signalVcomp. If the feedback signal Vfb1 is smaller than the minimum thresholdVL1, then the controller 42 asserts a control signal Up limit such thatthe up/down counter 44 increases the digital signal Sd to a maximumvalue immediately or at the maximum frequency so as to increase the slewrate of the third analog signal Vcomp. The controller 42 also provides afrequency adjustment signal Sfm for the oscillator 40 according to thecomparison result of the comparator 62 to adjust the frequency of theclock signal Clk. The greater the difference between the feedback signalVfb1 and the reference signal Vref1 is, the higher the frequency of theclock signal Clk will be, and this can increase the slew rate of thethird analog signal Vcomp and speed up the load transient response. Whenthe feedback signal Vfb1 is greater than the maximum threshold VH1 orsmaller than the minimum threshold VL1, the frequency of the clocksignal Clk will be increased to a maximum value by the frequencyadjustment signal Sfm to increase the sampling frequency of thecontroller 42 and the up/down counter 44. A pulse generator 64 generatesthe pulse signals Sp1-Sp5 as shown in FIG. 8 responsive to the clocksignal Clk, and provides the pulse signals Sp1-Sp5 to the multiplexer 60in turn in each period T of the clock signal Clk.

In the offset injector 26 shown in FIG. 7, the resistor Rof in FIG. 4 isreplaced by a variable resistor controlled by a switch, and theresistance of the variable resistor varies with the difference ΔVbetween the feedback signal Vfb1 and the reference signal Vref1. Thecurrent sources 46, 48, 50 and 52 supply fixed currents, so the currentIof passing through the variable resistor Rof is constant. In thisembodiment, the variable resistor Rof includes three resistors Ra, Rband Rc connected in series, and the resistors Ra, Rb and Rc areconnected in parallel with switches Ma, Mb and Mc, respectively. SignalsSa, Sb and Sc generated according to the difference ΔV control theswitches Ma, Mb and Mc, respectively, to adjust the resistance of thevariable resistor Rof, thereby generating the variable offset value Vofvarying with the difference ΔV for offsetting the first signal Va1 togenerate the second signal Va2.

FIG. 9 is a characteristic curve of the voltage variation rate dVa1/dtof the first signal Va1 of the DAC 24 shown in FIG. 7 versus the inputvoltage Vfb1 of the digital signal generator 22. When the feedbacksignal Vfb1 is increased to be greater than the threshold VH1, thedigital signal Sd is decreased at the maximum frequency, so the firstsignal Va1 has a maximum negative voltage variation rate −dVa1/dt_maxand the voltage variation rate of the first signal Va1 will not returnto the original level until the feedback signal Vfb1 is decreased to besmaller than the threshold VH2. Likewise, when the feedback signal Vfb1is decreased to be smaller than the threshold VL1, the digital signal Sdis increased at the maximum frequency, so the first signal Va1 has amaximum positive voltage variation rate dVa1/dt_max and the variationrate of the first signal Va1 will not return to the original level untilthe feedback signal Vfb1 is increased to be greater than the hysteresisthreshold VL2. In the embodiment shown in FIG. 7, as the number of thethresholds that are set increases, the curve of FIG. 9 approaches thecurve of FIG. 6.

FIG. 10 is a circuit diagram of a third embodiment for the mixed modecompensation circuit 20 shown in FIG. 3A. In the digital signalgenerator 22, a comparator 70 compares the feedback signal Vfb1 with athreshold VH1 to generate a comparison signal SB1, a comparator 72compares the feedback signal Vfb1 with a threshold VH2 to generate acomparison signal SB2, a comparator 74 compares the feedback signal Vfb1with the reference signal Vref1 to generate a comparison signal SB3, acomparator 76 compares the feedback signal Vfb1 with a threshold VL2 togenerate a comparison signal SB4, a comparator 78 compares the feedbacksignal Vfb1 with a threshold VL1 to generate a comparison signal SB5, acontroller 80 selects one of clock signals Clk1, Clk2, Clk3, Clk4 andClk5 as the clock signal Clk provided to an up/down counter 44 accordingto the comparison signals SB1, SB2, SB3, SB4 and SB5 in the way thatwhen the feedback signal Vfb1 is greater than the maximum threshold VH1or smaller than the minimum threshold VL1, the controller 80 selects theclock signal Clk1 of the maximum frequency to provide to the up/downcounter 44, the up/down counter 44 samples the comparison signal SB3responsive to the clock signal Clk and increase or decrease the digitalsignal Sd by one bit according to the sampling result in the way thatwhen the feedback signal Vfb1 is greater than the maximum threshold VH1or smaller than the minimum threshold VL1, the up/down counter 44decreases the digital signal Sd to a minimum value or increases thedigital signal Sd to a maximum value immediately or at the maximumfrequency responsive to the comparison signal SB1 or SB5 so as toincrease the slew rate of the third signal Vcomp, an oscillator 40provides the clock signal Clk1 of a frequency f, a frequency divider 82divides the frequency f of the clock signal Clk1 to generate the clocksignal Clk2 of a frequency f/2, a frequency divider 84 divides thefrequency f/2 of the clock signal Clk2 to generate the clock signal Clk3of a frequency f/4, a frequency divider 86 divides the frequency f/4 ofthe clock signal Clk3 to generate the clock signal Clk4 of a frequencyf/8, and a frequency divider 88 divides the frequency f/8 of the clocksignal Clk4 to generate the clock signal Clk5 of a frequency f/16. Inthis mixed mode compensation circuit, the characteristic curve of thevoltage variation rate dVa1/dt of the first signal Va1 of the DAC 24versus the input voltage Vfb1 of the digital signal generator 22 is asshown FIG. 9.

In FIG. 10, the LPF 28 includes a low-bandwidth operational amplifier 90having a non-inverting input terminal to receive the second signal Va2from the offset injector 26 and an inverting input terminal electricallyconnected to the output terminal Vcomp of the LPF 28, a resistor R5 anda compensation capacitor C3 serially connected between the outputterminal of the operational amplifier 90 and the output terminal Vcompof the LPF 28 to stabilize the third signal Vcomp, a transistor M5connected between a power terminal Vcc and the output terminal Vcomp ofthe LPF 28 and having a gate electrically connected to the outputterminal of the operational amplifier 90, and a resistor R6 connectedbetween the output terminal Vcomp of the LPF 28 and a ground terminalGND.

Although FIGS. 4, 7 and 10 show embodiments of the mixed modecompensation circuit 20 corresponding to FIG. 3A, it can be readilyunderstood that the mixed mode compensation circuits 20 a-20 g shown inFIGS. 3B-3H can be embodied by using the circuit components in the mixedmode compensation circuit 20 shown in FIGS. 4, 7 and 10.

FIG. 11 illustrates the effect of the present invention, in whichwaveforms 92 and 96 are the output voltage Vo of a power converter andthe signal Vcomp, respectively, that are generated by using the gm typeanalog compensation circuit 14 shown in FIG. 2, while waveforms 94 and98 are the output voltage Vo of a power converter and the third signalVcomp, respectively, that are generated by using the mixed modecompensation circuit 20 of the present invention, and are almost thesame as the waveforms 92 and 96 generated by using the gm type analogcompensation circuit 14. Moreover, when a load transient occurs at timet1, the mixed mode compensation circuit 20 also has a good transientresponse. Therefore, the mixed mode compensation circuit 20 can indeedreplace the conventional analog compensation circuit 14. The mixed modecompensation circuit 20 can reduce the frequency of the clock signal Clkto achieve the same effect of stabilizing the signal Vcomp as thatprovided by large capacitors C1 and C2 in the analog compensationcircuit 14, and thus the mixed mode compensation circuit 20 needs notuse large capacitors C1 and C2, so it can be easily integrated into acontrol IC to reduce the number of the pins. Due to combining an analogcircuit and a digital circuit together, the mixed mode compensationcircuit 20 is simpler and thereby occupies a smaller chip area, andeliminates the need for a complex DSP algorithm as compared to thedigital compensation circuit. This can simplify the design and reducethe costs.

FIG. 12A shows a mixed mode compensation circuit 120 according toanother embodiment of the present invention. FIGS. 12B-12E show mixedmode compensation circuits 120 a-120 d according to other embodiments ofthe present invention, which are variations of the mixed modecompensation circuit 120.

Referring to FIG. 12A, the mixed mode compensation circuit 120 includesa digital signal generator 122, an adder 123, a digital-to-analogconverter (DAC) 124, a digital offset injector 126, and a digital filter128, wherein the digital signal generator 122 functions as a first polegenerator/compensator, the digital offset injector 126 functions as azero generator/compensator, and the digital filter 128 functions as asecond pole generator/compensator. This embodiment is different from theembodiment of FIG. 3A in that the zero generator/compensator and thesecond pole generator/compensator are embodied by digital circuits andare located before the DAC 124. However, it is not necessary for both ofthe zero generator/compensator and the second pole generator/compensatorto be embodied by digital circuits; one of them, for example but notlimited to the second pole generator/compensator, can be embodied by ananalog circuit such as a low-pass filter. In this case the digitalfilter 128 can be replaced by a LPF 129, as shown by FIG. 12B.

Referring back to FIG. 12A, the digital signal generator 122 generates adigital signal Sd according to a reference signal Vref1 and a feedbacksignal Vfb1 related to an output voltage of a power converter. Thedigital offset injector 126 provides a variable offset value accordingto another output signal Sfb from the digital signal generator 122,which will be described in detail later. The digital filter 128 filtersthe output signal So from the digital offset injector 126 to generate afiltered offset value Sfo. The adder 123 adds the digital signal Sd withthe filtered offset value Sfo to generate a digital signal Sd1, which isconverted by the DAC 124 to the signal Vcomp.

Note that it may not be necessarily required to generate/compensate twopoles and one zero. In some applications, it may only be required togenerate/compensate one pole, or one pole and one zero, or two poles.When it is only required to generate/compensate one pole, the circuits123, 126 and 128 can be omitted, and it will result in a circuit asshown in FIG. 3B. When it is only required to generate/compensate onepole and one zero, the digital filter 128 can be omitted, and it willresult in a circuit as shown in FIG. 12C. When it is only required togenerate/compensate two poles, the adder 123 and the digital offsetinjector 126 can be omitted, and it will result in a circuit as shown inFIG. 12D. Furthermore, please note that the location of the digitalfilter 128 is not limited to that as shown in FIG. 12A; for example, thedigital filter 128 can be located after the adder 123 (coupled to theoutput of the adder 123), as shown in FIG. 12E. In this case, the signalSfd1 is a signal obtained by filtering the signal Sd1, so the signalSfd1 can be regarded as a signal related to the signal Sd1.

In addition to the above arrangements, as an alternative, the additionof digital signals can be equivalently achieved by first converting thedigital signals to analog signals and then adding the converted analogsignals. As shown in FIGS. 12F-12G, the output signal Sd from thedigital signal generator 122 and the output signal So from the digitaloffset injector 126 are converted to analog signals by the DAC 124 andDAC 124 a respectively, and then added together. The difference betweenFIGS. 12F and 12G is the location of the LPF 129 (in FIG. 12F, theoutput signal from the LPF 129 is a signal obtained by filtering thesignal outputted from the DAC 124, so the output signal from the LPF 129can be regarded as a signal related to the signal outputted from the DAC124).

FIG. 13 shows an embodiment of the digital signal generator 122. Asshown in the figure, in this embodiment, the digital signal generator122 includes a successive approximation register analog-to-digitalconverter (SAR-ADC) 132 and an up/down counting circuit 134. The SAR-ADC132 generates an up/down signal U/D according to the feedback signalVfb1 and the reference signal Vref1. The up/down signal U/D controls theup/down counting circuit 134 so that the output signal of the up/downcounting circuit 134 (which is the digital signal Sd) increases ordecreases accordingly. The up/down counting circuit 134 operatesaccording to a clock signal CLK. In the embodiments of FIGS. 12A-12C and12E, optionally, the digital offset injector 126 may feedback controlthe frequency of the clock signal CLK, for example by generating theclock signal CLK by the digital offset injector 126, or by sending asignal to control an oscillator inside the digital signal generator 122which generates the clock signal CLK.

The SAR-ADC 132 further generates another output signal Sfb. The signalSfb is a digital signal corresponding to the feedback signal Vfb1, orcorresponding to a difference between the feedback signal Vfb1 and thereference signal Vref1, which will be explained in detail in thefollowing.

FIGS. 14A-14D show four embodiments of the SAR-ADC 132. In theembodiment of FIG. 14A, the reference signal Vref1 is a digital signaland the SAR-ADC 132 includes a comparator 144, a controller and codegenerator 146, and a DAC 148. The comparator 144 compares the feedbacksignal Vfb1 with an analog feedback signal generated by the DAC 148; inresponse to the output signal of the comparator 144, the controller andcode generator 146 generates an N-bit digital code, which is sent to theDAC 148 so that the DAC 148 generates the analog feedback signalcorresponding to the N-bit digital code. Thus, in a way, the N-bitdigital code is a digital signal converted from the feedback signalVfb1, so the circuit is called SAR-ADC. The controller and codegenerator 146 further generates a digital signal Sfb, wherein thedigital signal Sfb can be the same or different from the N-bit digitalcode, that is, the digital signal Sfb can be N-bit or any other numberof bits, and can be expressed by the same format as the N-bit digitalcode or by any other format. In a first embodiment, the digital signalSfb also corresponds to the feedback signal Vfb1, and it can be viewedas a digital expression of the feedback signal Vfb1. By the feedbackloop formed by the comparator 144, the controller and code generator146, and the DAC 148, the digital signal Sfb can be an accurate digitalnumber representing the feedback signal Vfb1. In addition, thecontroller and code generator 146 further receives the reference signalVref1, and it generates an up/down signal U/D according to a comparisonbetween the feedback signal Vfb1 and the reference signal Vref1. Morespecifically, because the reference signal Vref1 is a digital signal,and both the N-bit digital code and the digital signal Sfb are digitalexpressions of the feedback signal Vfb1, the comparison can be done bycomparing the reference signal Vref1 with either the N-bit digital codeor the digital signal Sfb in a digital manner, for example bysubtracting one from the other. When the feedback signal Vfb1 is greaterthan the reference signal Vref1, that is, when the N-bit digital code orthe digital signal Sfb is greater than the reference signal Vref1, theup/down signal U/D instructs the up/down counting circuit 134 toincrease the digital signal Sd, for example by digital number one. Whenthe feedback signal Vfb1 is smaller than the reference signal Vref1,that is, when the N-bit digital code or the digital signal Sfb issmaller than the reference signal Vref1, the up/down signal U/Dinstructs the up/down counting circuit 134 to decrease the digitalsignal Sd, for example by digital number one.

In a second embodiment, the digital signal Sfb corresponds to adifference between the feedback signal Vfb1 and the reference signalVref1, and it can be viewed as a digital expression of the differencebetween the feedback signal Vfb1 and the reference signal Vref1. Likely,because the reference signal Vref1 is a digital signal, and the N-bitdigital code is a digital expression of the feedback signal Vfb1, thedifference can be obtained by comparing the reference signal Vref1 withthe N-bit digital code in a digital manner, for example by subtractingone from the other. Or, the digital signal Sfb can be a coded expressionof the difference. The rest of the circuit operates similar to the firstembodiment wherein the digital signal Sfb corresponds to the feedbacksignal Vfb1.

In the embodiment of FIG. 14B, the reference signal Vref1 is a digitalsignal which is inputted to the DAC 148 as an initial code number.Similarly, the digital signal Sfb can correspond to the feedback signalVfb1 or correspond to the difference between the feedback signal Vfb1and the reference signal Vref1 (that is, the digital signal Sfb can be adigital expression of the feedback signal Vfb1 or a digital expressionof the difference between the feedback signal Vfb1 and the referencesignal Vref1). The rest of the circuit operates similar to theembodiment of FIG. 14A.

In the embodiment of FIG. 14C, the reference signal Vref1 is an analogsignal and the SAR-ADC 132 includes an error amplifier 141, a comparator142, a controller and code generator 146, and a DAC 148. The erroramplifier 141 compares the feedback signal Vfb1 with the referencesignal Vref1 to generate an error amplified signal. The comparator 142,the controller and code generator 146, and the DAC 148 form a SAR whichoperates similar to the embodiment of FIG. 14A, except that the digitalsignal Sfb is a digital expression of the difference between thefeedback signal Vfb1 and the reference signal Vref1.

In the embodiment of FIG. 14D, the reference signal Vref1 is an analogsignal and the SAR-ADC 132 includes two comparators 143 and 144, acontroller and code generator 146, and a DAC 148. The comparator 143compares the analog feedback signal generated by the DAC 148 with thereference signal Vref1, and the result is sent to the controller andcode generator 146. This embodiment operates similar to the embodimentof FIG. 14A, except that the controller and code generator 146 receivesthe output signal of the comparator 143 instead of a digital referencesignal Vref1.

FIG. 15 shows an embodiment of the up/down counting circuit 134. Theup/down counting circuit 134 includes a controller 152 and an up/downcounter 154. The controller 152 is controlled by the up/down signal U/D,and it operates by a frequency determined by a clock signal CLK. Therelationship between the controller 152 and an up/down counter 154 issimilar to the relationship between the controller 42 and an up/downcounter 44, and therefore is not redundantly repeated here.

FIG. 16A shows an embodiment of the digital offset injector 126. Asexplained in the above, the digital offset injector 126 functions as azero generator/compensator by providing a variable offset value, whereinthe variable offset value is related to the difference between thefeedback signal Vfb1 and the reference signal Vref1. Therefore, thedigital offset injector 126 can be designed in many ways as long as itcan generate a digital number or code which corresponds to, or is adigital expression, of α·(Vfb1−Vref1), wherein α is a positive realnumber indicating a scale factor corresponding to the transconductanceof the transconductance amplifier 16 multiplied by the resistance of theresistor R3 in the analog circuit of FIG. 2. As shown in FIG. 16A, inone embodiment, the digital offset injector 126 can be embodied as adigital multiplier which multiplies the digital signal Sfb by a factor βwhich is a positive real number to generate the variable offset valueSo. (Or, if the factor β is a positive real number smaller than 1, thedigital multiplier can be a divider which divides the digital signal Sfbby a factor 1/(β.) In this embodiment the digital signal Sfb correspondsto, or is a digital expression of the difference between the feedbacksignal Vfb1 and the reference signal Vref1. The factor β can be given bya designer of the mixed mode compensation circuit. The variable offsetvalue So outputted from the digital multiplier is equal to β·Sfb, whichcorresponds to α·(Vfb1−Vref1).

In another embodiment as shown in FIG. 16B, wherein the digital signalSfb corresponds to, or is a digital expression of the feedback signalVfb1, the digital offset injector 126 includes an adder/subtractor 162and a digital multiplier 164. The adder/subtractor 162 subtracts adigital signal Sref1 from the digital signal Sfb, wherein the digitalsignal Sref1 corresponds to, or is a digital expression of the referencesignal Vref1. The digital multiplier 164 multiplies the differencebetween the digital signal Sfb and the digital signal Sref1 by a factorβ. The variable offset value So outputted from the digital multiplier isequal to β·(Sfb−Sref1), which corresponds to α·(Vfb1−Vref1).

Besides the above embodiments, the digital offset injector 126 can beembodied by many other ways; for example, the digital offset injector126 can be embodied as a memory with different pre-stored offset valuesat different addresses, and the digital signal Sfb can be the address,or can be used to generate the address of the memory, as shown in FIG.16C. The digital signal Sfb can correspond either to the feedback signalVfb1 or to the difference between the feedback signal Vfb1 and thereference signal Vref1.

FIGS. 16D-16F shows three other embodiments of the digital offsetinjector 126. Referring to FIG. 16D, the digital offset injector 126 ofthis embodiment includes a digital multiplier 164 and a frequencydivider 166. The digital multiplier 164 operates in a manner similar tothe embodiment of FIG. 16A. The frequency divider 166 receives a clocksignal CLK_132, which is the clock signal by which the SAR-ADC 132operates (for example, by which the DAC 148 of the SAR-ADC 132operates). The frequency divider 166 divides the clock signal CLK_132 togenerate a frequency-divided clock signal CLK. The generated clocksignal CLK has a different frequency f1, f2, . . . , depending on thedigital signal Sfb. That is, the frequency of the clock signal CLK isdependent on the digital signal Sfb. The clock signal CLK is sent to theup/down counting circuit 134 (referring to FIGS. 12A-12C, 12E, 13 and15) so that the controller 152 operates according to this clock signalCLK. In this way, the digital offset injector 126 modulates thefrequency by which the up/down counting circuit 134 operates, whichprovides an effect similar to the capacitor C1 in FIG. 2.

FIGS. 16E and 16F correspond to FIGS. 16B and 16C, except that thedigital offset injector 126 also includes a frequency divider 166 togenerate a frequency-divided clock signal CLK. The frequency divider 166operates similarly to the embodiment of FIG. 16D. Note that in theembodiment of FIG. 16E, instead of dividing the clock signal CLK_132according to the digital signal Sfb as shown, as an alternative (notshown, but referring to FIG. 16H), the frequency divider 166 can dividethe clock signal CLK_132 according to the output from theadder/subtractor 162. In this alternative case, because the digitalsignal Sref1 corresponds to the reference signal Vref1 which is a knownsignal, the frequency of the clock signal CLK is still dependent on thedigital signal Sfb.

FIGS. 16G-16I shows three other embodiments of the digital offsetinjector 126. Referring to FIG. 16G, the digital offset injector 126 ofthis embodiment includes a digital multiplier 164 and a DAC 168. Thedigital multiplier 164 operates in a manner similar to the embodiment ofFIG. 16A. The DAC 168 converts the digital signal Sfb to an analogsignal, which may be a current signal or a voltage signal. In addition,the digital signal generator 122 includes an oscillator (OSC) 136, whichmay be a current-controlled oscillator or a voltage-controlledoscillator, depending on whether the DAC 168 generates a current signalor a voltage signal. The signal generated by the DAC 168 controls theOSC 136 to determine the frequency of the clock signal CLK generated bythe OSC 136. The clock signal CLK is what the up/down counting circuit134 operates by. In this way, the digital offset injector 126 also canmodulate the operation frequency of the up/down counting circuit 134 toprovide an effect similar to the capacitor C1 in FIG. 2.

FIGS. 16H and 161 correspond to FIGS. 16B and 16C, except that thedigital offset injector 126 also includes a DAC 168 and the digitalsignal generator 122 also includes an OSC 136. The DAC 168 and the OSC136 operate similarly to the embodiment of FIG. 16G. Note that in theembodiment of FIG. 16H, the DAC 168 converts the output from theadder/subtractor 162 to the analog signal for controlling the OSC 136.In an alternative arrangement, the DAC 168 can convert the digitalsignal Sfb to the analog signal for controlling the OSC 136.

FIGS. 17A and 17B shows two embodiments of the digital filter 128.Referring to FIG. 17A, in a simple form, the digital filter 128 can beembodied as a D flip-flop. Taking the embodiment of FIG. 12E forexample, wherein the digital filter 128 is connected between the adder123 and the DAC 124, to receive the digital signal Sd1 and generate afiltered digital signal Sfd1, the digital signal Sd1 can be inputted tothe D flip-flop. The D flip-flop operates according to a clock signalCLK_128, which has a slower frequency than the clock signal CLK_132 bywhich the SAR-ADC 132 operates, and more preferably slower than theclock signal CLK by which the up/down counting circuit 134 operates.(Note that the numbers 128 and 132 are irrelevant to the ratio betweenthe clock signals; they only indicate the circuits using these clocksignals.) Because the D flip-flop operates by a slower frequency, itprovides an effect similar to the capacitor C2 in FIG. 2.

Referring to FIG. 17B, in a more sophisticated form, the digital filter128 can be embodied as a moving average circuit. Also taking theembodiment of FIG. 12E for example, the moving average circuit receivesthe digital signal Sd1 and generates a filtered digital signal Sfd1 byobtaining a moving average of the digital signal Sd1. There are manyways to calculate a moving average; one example is as below:

Sfd1 _(t)=sum_(t)/n=(sum_((t−1))−Sfd1 _((t−1))+Sfd_(t))/n  [EQ-3]

wherein Sfd1 _(t) and Sfd1 _((t−1)) are the digital signal Sfd1 at thepresent time point and the digital signal Sfd1 at the previous timepoint, respectively; Sfd_(t) is the digital signal Sfd at the presenttime point; Sum_(t) and Sum_((t−1)) are the accumulated sum at thepresent time point and the accumulated sum at the previous time point,respectively; and n is the divider which is typically a positive integerto determine the smoothness and the approaching speed of the movingaverage.

Although FIGS. 17A and 17B takes the embodiment of FIG. 12E for example,it can be readily understood that the circuit of FIG. 17A or 17B isapplicable to other embodiments.

The present invention has been described in considerable detail withreference to certain preferred embodiments thereof. It should beunderstood that the description is for illustrative purpose, not forlimiting the scope of the present invention. Those skilled in this artcan readily conceive variations and modifications within the spirit ofthe present invention. For example, other circuits or devices, such asbut not limited to a switch or the like, can be added between twocircuits or devices shown to be in direct connection is the embodiments,as long as these added circuits or devices do not affect the primaryfunction. In view of the foregoing, the spirit of the present inventionshould cover all such and other modifications and variations, whichshould be interpreted to fall within the scope of the following claimsand their equivalents. An embodiment or a claim of the present inventiondoes not need to achieve all the objectives or advantages of the presentinvention. The title and abstract are provided for assisting searchesbut not for limiting the scope of the present invention.

1-26. (canceled)
 27. A mixed mode compensation circuit for a powerconverter, comprising: a digital signal generator for generating a firstdigital signal and a second digital signal according to a referencesignal and an output voltage feedback signal which is related to anoutput voltage of the power converter; a digital offset injector coupledto the digital signal generator, for generating a variable offsetaccording to the second digital signal; a first digital-to-analogconverter coupled to the digital signal generator, for converting thefirst digital signal into a first analog signal; a seconddigital-to-analog converter coupled to the digital signal generator, forconverting the second digital signal into a second analog signal; and anadder for adding the first analog signal and the second analog signal oradding a signal related to the first analog signal and the second analogsignal.
 28. The mixed mode compensation circuit of claim 27, furthercomprising: a low-pass filter coupled between the firstdigital-to-analog converter and the adder or coupled to the output ofthe adder.
 29. The mixed mode compensation circuit of claim 27, whereinthe digital offset injector generates a digital number or codecorresponding to α·(Vfb1−Vref1), wherein a is a positive real number;Vfb1 is the output voltage feedback signal; and Vref1 is the referencesignal.
 30. The mixed mode compensation circuit of claim 27, wherein thedigital offset injector includes a digital multiplier for multiplyingthe second digital signal by a factor β to generate the variable offset,wherein β is a positive real number.
 31. The mixed mode compensationcircuit of claim 27, wherein the digital offset injector includes: anadder/subtractor subtracting a third digital signal corresponding to thereference signal from the second digital signal to obtain a difference;a digital multiplier multiplying the difference by a factor β togenerate the variable offset, wherein β is a positive real number. 32.The mixed mode compensation circuit of claim 27, wherein the digitaloffset injector includes: a memory having a plurality of addressesstoring a plurality of offsets, and the second digital signal being ordetermining one of the addresses; and a digital-to-analog converter forconverting the second digital signal into an analog signal to control afrequency of the oscillator.
 33. The mixed mode compensation circuit ofclaim 27, wherein the digital offset injector feedback controls a clocksignal of the digital signal generator.
 34. The mixed mode compensationcircuit of claim 33, wherein the digital signal generator furthercomprises an oscillator for generating the clock signal, and the digitaloffset injector includes: a digital multiplier multiplying the seconddigital signal by a factor β to generate the variable offset, wherein βis a positive real number; and a digital-to-analog converter forconverting the second digital signal into an analog signal to control afrequency of the oscillator.
 35. The mixed mode compensation circuit ofclaim 33, wherein the digital signal generator further comprises anoscillator for generating the clock signal, and the digital offsetinjector includes: an adder/subtractor subtracting a third digitalsignal corresponding to the reference signal from the second digitalsignal to obtain a difference; a digital multiplier multiplying thedifference by a factor β to generate the variable offset, wherein β is apositive real number; and a digital-to-analog converter for convertingthe second digital signal or the third digital signal into an analogsignal to control a frequency of the oscillator.
 36. The mixed modecompensation circuit of claim 33, wherein the digital signal generatorfurther comprises an oscillator for generating the clock signal, and thedigital offset injector includes: a memory having a plurality ofaddresses storing a plurality of offsets, and the second digital signalbeing or determining one of the addresses; and a digital-to-analogconverter for converting the second digital signal into an analog signalto control a frequency of the oscillator.
 37. The mixed modecompensation circuit of claim 27, wherein the digital signal generatorincludes: a SAR-ADC for generating an up/down signal according to theoutput voltage feedback signal and the reference signal; and an up/downcounter having an output controlled by the up/down signal tocorrespondingly increase or decrease.
 38. The mixed mode compensationcircuit of claim 37, wherein the SAR-ADC operates according to a firstclock signal and the up/down counter operates according to a secondclock signal, and wherein the digital offset injector includes: adigital multiplier multiplying the second digital signal by a factor βto generate the variable offset, wherein β is a positive real number;and a frequency divider circuit for dividing a frequency of the firstclock signal according to the second digital signal to generate thesecond clock signal.
 39. The mixed mode compensation circuit of claim37, wherein the SAR-ADC operates according to a first clock signal andthe up/down counter operates according to a second clock signal, andwherein the digital offset injector includes: an adder/subtractorsubtracting a third digital signal corresponding to the reference signalfrom the second digital signal to obtain a difference; a digitalmultiplier multiplying the difference by a factor β to generate thevariable offset, wherein β is a positive real number; and a frequencydivider circuit for dividing a frequency of the first clock signalaccording to the second digital signal or the third digital signal togenerate the second clock signal.
 40. The mixed mode compensationcircuit of claim 37, wherein the SAR-ADC operates according to a firstclock signal and the up/down counter operates according to a secondclock signal, and wherein the digital offset injector includes: a memoryhaving a plurality of addresses storing a plurality of offsets, and thesecond digital signal being or determining one of the addresses; and afrequency divider circuit for dividing a frequency of the first clocksignal according to the second digital signal to generate the secondclock signal. 41-56. (canceled)